The present invention relates generally electronic circuits, and more specifically, to an inverter circuit.
Recent years have witnessed an increased demand for miniature and high-performance electronic devices. This demand has been primarily addressed with the evolution of integrated circuits (ICs) designed using very large scale integration (VLSI). Using VLSI, a single IC can have hundreds of thousands of transistors. This is achieved by miniaturizing transistors to sizes on the order of about 50 nanometer (nm) or less.
Although, reduced transistor size leads to increased processing power, it also can lead to increased power consumption. Power is classified as either static or dynamic. Static power consumption may be determined by calculating a product of a supply voltage provided to a transistor of the IC and a magnitude of direct current (DC) that includes both through current and leakage current, while dynamic power consumption, which includes capacitive power consumption, is determined by calculating a product of a load capacitance, a square of the supply voltage, and a toggle frequency.
Additionally, dynamic power consumption also includes power dissipation resulting from short circuits in the ICs when transistors in an inverter circuit switch state. For example, when an inverter circuit that includes p-channel metal oxide semiconductor (PMOS) and n-channel metal oxide semiconductor (NMOS) transistors switches state, both PMOS and NMOS transistors conduct current for a short duration of time. This simultaneous conduction of current results in a short-circuit DC current of considerable magnitude that flows through both the PMOS and NMOS transistors when an output is around one half of the supply voltage. The short-circuit DC current does not contribute to switching the capacitive loads and results in short-circuit power dissipation.
Various inverter circuits have been designed to reduce short-circuit power consumption. FIG. 1 is a schematic circuit diagram of one such conventional inverter circuit 100. The inverter circuit 100 includes first and second transistors 102 and 104, first and second capacitors 106 and 108, first and second diodes 110 and 112, and first and second resistors 114 and 116.
First terminals of the first and second resistors 114 and 116 receive an input voltage Vin. The first terminal of the first resistor 114 is connected to a first terminal of the first diode 110 and a second terminal of the first resistor 114 is connected to a second terminal of the first diode 110. The first terminal of the second resistor 116 is connected to a second terminal of the second diode 112 and a second terminal of the second resistor 116 is connected to a first terminal of the second diode 112. The second terminals of the first and second resistors 114 and 116 are connected to first terminals of the first and second capacitors 106 and 108, respectively, and second terminals of the first and second capacitors 106 and 108 are connected to ground.
A source of the first transistor 102 is connected to a supply voltage Vdd, and a gate of the first transistor 102 is connected to the first terminal of the first capacitor 106. A source of the second transistor 104 is connected to ground, a gate of the second transistor 104 is connected to the first terminal of the second capacitor 108, and a drain of the second transistor 104 is connected to a drain of the first transistor 102.
The first diode 110 and the first resistor 114 are connected in parallel between an input terminal of the inverter circuit 100 (node at which Vin is provided) and the gate of the first transistor 102, while the second diode 112 and the second resistor 116 are connected in parallel between the input terminal of the inverter circuit 100 and the gate of the second transistor 104. The first and second resistors 114 and 116 have a high resistance. Thus, the equivalent resistance of the first and second resistors 114 and 116 is reduced when either of the first and second diodes 110 and 112 is reverse-biased. This in turn increases a conductance for a conduction path between the input terminal of the inverter circuit 100 and the gates of the first and second transistors 102 and 104 when the diode is reverse-biased. However, when either of the first and second diodes 110 and 112 is forward-biased, the low resistance and high conductance for the conduction path between the input terminal of the inverter circuit 100 and the gates of the first and second transistors 102 and 104 remains undisturbed. Higher equivalent resistance when either of the first and second diodes 110 and 112 is reverse-biased slows the charging and discharging of the gates of the first and second transistors 102 and 104, which reduces short-circuit current and short-circuit power dissipation.
Although the inverter circuit 100 reduces short-circuit current and power dissipation, the magnitude of the dynamic current flowing through the inverter circuit 100 is high, which leads to an overall increase in dynamic power dissipation. Further, the slowing of the charging and discharging of the gates of the first and second transistors 102 and 104 leads to slow switching speed, which increases the transistor delay and degrades performance. Furthermore, the additional resistors and diodes, i.e., the first and second resistors 114 and 116 and the first and second diodes 110 and 112, increase on-chip area, which increases the overall cost of the IC.
Therefore, it would be advantageous to have an inverter circuit that has low short-circuit power consumption and fast switching, a small footprint, and overcomes the above-mentioned limitations of conventional inverter circuits.